| Title |
Towards a High-Speed Programmable Hardware Architecture for the Network Transport Layer |
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| Authors |
Kimiya Mohammadtaheri, Nachiket Kapre, Mina Tahmasbi Arashloo |
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| Abstract |
As network speeds keep increasing, there is a growing interest in accelerating network functions using programmable Network Interface Cards (NICs). Transport protocols play a critical role in managing traffic flow and resource allocation, yet their high-speed implementation on NICs remains a challenge due to the complexity of stateful operations and the need for low-level hardware expertise. This project introduces a high-level programming platform called MTP that allows users to specify transport protocols without concerning themselves with hardware-specific details. We will then introduce a compiler that can translate this code to a low level hardware design. We will then explain the general structure of such hardware design and the challenges of mapping the components of the high-level platform to hardware and leveraging the capabilities of hardware. |
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| Date |
February 9, 2025 |
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| Report |
CS-2025-01 (395 kB PDF) |
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