Please note: This PhD seminar will take place online.
Gaetano Coccimiglio, PhD candidate
David R. Cheriton School of Computer Science
Supervisors: Professors Trevor Brown, Peter Buhr
Utilizing hardware transactional memory (HTM) in conjunction with non-volatile memory (NVM) to achieve persistence is quite difficult and somewhat awkward due to the fact that the primitives utilized to write data to NVM will abort HTM transactions. We present several persistent hybrid transactional memory (HyTM) that, perhaps counterintuitively, utilize an HTM fast path primarily to read or acquire fine-grained locks which protect data items. Our implementations guarantee durable linearizable transactions and the STM path satisfies either weak progressiveness or strong progressiveness. We discuss the design choices related to the differing progress guarantees and we examine how these design choices impact performance. We evaluate our persistent HyTM implementations using various microbenchmarks. Despite the challenges and apparent awkwardness of using current implementations of HTM to achieve persistence, our implementations achieve up to 10x improved performance compared to the existing state of the art persistent STMs and up to 2.6x improved performance compared to the existing state of the art persistent HyTMs.