Lecture 10 - Depth Reduction III

In the last lecture, we saw how to reduce the depth of any circuit of size s computing a polynomial of degree d to a circuit of size poly(s,d) and depth O(logd(logs+logd)) computing the same polynomial.

In particular, we have the following conclusion:


Corollary 1: If f is a polynomial in n variables of degree d=poly(n) such that f cannot be computed by any circuit of size poly(n) and depth O(log2n), then f is not in VP.


In this lecture, we will see how to reduce the depth even further, all the way to depths 4 and 3, albeit with a siginificant increase in the size of the circuit. This is useful for (at least) two reasons:

  1. Circuits of constant depth should (in principle) be easier to analyze.
  2. One could hope to get exponential lower bounds on the size of circuits of constant depth computing a hard polynomial.

Whenever we talk about a constant depth circuit (or formula), we will always assume that the circuit has alternating layers of sum and product gates, having the top gate being a sum gate. This convention makes sense as we want to talk about circuits that can compute several polynomials, as opposed to circuits which only compute reducible polynomials.

Note that a depth 2 circuit, denoted by ΣΠ circuit, is simply a sum of monomials, and therefore it is easy to give an exponential lower bound on the size of a ΣΠ circuit computing a hard polynomial. Since every polynomial is uniquely defined by its monomials (and their coefficients), the size of a ΣΠ circuit computing a polynomial is at least the number of monomials in the polynomial. The hard polynomials in this case are all polynomials with exponentially many monomials. A depth 2 circuit is also known as the sparse representation of a polynomial.

Since the complexity of a polynomial in depth 2 circuits is completely understood, and even very easy polynomial families require exponential size depth 2 circuits, we cannot hope to have efficient depth reduction to depth 2 circuits. So, the next question would be: can we reduce the depth of a circuit to depth 3 or 4?

We begin with the surprising result that the answer is yes, for both depth 4 and depth 3 circuits! The first depth reduction to depth 4 was given by Agrawal and Vinay in 2008, and the first depth reduction to depth 3 was given by Gupta, Kamath, Kayal, and Saptharishi in 2014.

Depth Reduction to Depth 4

We begin by showing how to reduce the degree of a circuit all the way to depth 4. We denote a homogeneous depth 4 circuit by hom-ΣΠΣΠ circuit. Moreover, we denote by hom-ΣΠ[d/t]ΣΠ[t] a homogeneous depth 4 circuit where the top product gate has fanin d/t and the bottom product gate has fanin t. The top fanin of the circuit is the fanin of the top sum gate.


Theorem 1 ([AV'08, Koi'12, Tav'15]): Let f be a form in n variables of degree d computed by a homogeneous circuit of size s. Then, for any 0<td, there is a hom-ΣΠ[d/t]ΣΠ[t] circuit of size sO(t+d/t) and top fanin sO(d/t) computing f.


Proof: Once again, we can assume w.l.o.g. that sn. By VSBR, we know that there is a homogeneous circuit Ψ of size poly(s,d) and depth O(log(d)) computing f, with the following properties:

  1. The circuit Ψ has alternating layers of sum and product gates.
  2. The top gate of Ψ is a sum gate.
  3. Each product gate vΨ has fanin at most 5, and each child u of v satisfies deg(u)deg(v)/2.

We will now show how to convert Ψ into a hom-ΣΠ[d/t]ΣΠ[t] circuit.

Depth Reduction to Depth 3

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