2007 Oct 02 at 16:30
David Patterson, Pardee Professor of Computer Science, University of California at Berkeley
The sequential processor era is now officially over, as the IT industry has bet its future on multiple processors per chip. This shift toward increasing parallelism is not a triumphant stride forward based on breakthroughs in novel software and architectures for parallelism; instead, this plunge into parallelism is actually a retreat from even greater challenges that thwart efficient silicon implementation of traditional uniprocessor architectures.
The IT industry is urgently facing perhaps its greatest challenge in 50 years, giving researchers the once-in-a-lifetime chance to reset the foundations of computing, provided we can deliver on the overarching goal to make it easy to write programs that execute efficiently on highly parallel computing systems.
A diverse group of University of California at Berkeley researchers from many backgrounds circuit design, computer architecture, massively parallel computing, computer-aided design, embedded hardware and software, programming languages, compilers, scientific programming, and numerical analysis met for two years to discuss this topic from these many angles. This talk and a technical report are the result. (See view.eecs.berkeley.edu)
We concluded that sneaking up on the problem of parallelism the way industry is planning is likely to fail, and we desperately need a new solution for parallel hardware and software. Here are some of our recommendations:
The target should be 1000s of cores per chip, as these chips are built from processing elements that are the most efficient in MIPS (Million Instructions per Second) per watt, MIPS per area of silicon, and MIPS per development dollar.
Instead of traditional benchmarks, use 13 Dwarfs to design and evaluate parallel programming models and architectures. (A dwarf is an algorithmic method that captures a pattern of computation and communication.)
Autotuners should play a larger role than conventional compilers in translating parallel programs.
To maximize programmer productivity, future programming models must be more human-centric than the conventional focus on hardware or applications or formalisms.
Traditional operating systems will be deconstructed and operating system functionality will be orchestrated using libraries and virtual machines.
To explore the design space rapidly, use system emulators based on Field Programmable Gate Arrays that are highly scalable and low cost. (see ramp.eecs.Berkeley.edu)
David Patterson is the Pardee Professor of Computer Science at the University of California at Berkeley, which he joined after graduating from UCLA in 1977. Daves research style is to identify critical questions for the IT industry and gather inter-disciplinary groups of faculty and graduate students to answer them. The answer is typically embodied in demonstration systems, and these demonstration systems are later mirrored in commercial products. The best known projects were on Reduced Instruction Set Computers, Redundant Array of Inexpensive Disks, and Networks of Workstations.
One measure of the success of projects is the list of awards won by Dave and his teammates: the C & C Prize, the IEEE von Neumann Medal, the IEEE Johnson Storage Award, the SIGMOD Test of Time award, and the Katayanagi Prize. He was also named fellow of ACM, IEEE, AAAS, the Computer Museum, the National Academy of Engineering, the National Academy of Sciences, and the Silicon Valley Engineering Hall of Fame.
In his spare time, he co-authored five books, including two with John Hennessy in computer architecture that are in their fourth editions. Dave also served as President of ACM, as chair of the Computing Research Association, and as chair of the Computer Science Division at UC Berkeley.